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Ninth Great Lakes Symposium on VLSI
An Incremental Floorplanner
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
Jim Crenshaw, Motorola
Majid Sarrafzadeh, Northwestern University
Prithviraj Banerjee, Northwestern University
Pradeep Prabhakaran, Compaq-Digital
One of the foremost problems in physical design for deep-submicron circuits is the need for estimates that depend on future decisions. Estimation of area, timing, and coupling are required..We propose a novel floorplanner, with a new wiring metric, which can be updated quickly in small increments. This provides tools with a way to influence the floorplan as they make changes without a large running time penalty. We provide experimental results that show the incremental approach to be generally 5 times faster than full floorplanning while maintaining good estimates.
Citation:
Jim Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran, "An Incremental Floorplanner," glsvlsi, pp.248, Ninth Great Lakes Symposium on VLSI, 1999
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