Ninth Great Lakes Symposium on VLSI VHDL Design of a Test Processor Based on Mixed-Mode Test Generation Ann Arbor, Michigan March 04-March 06 ISBN: 0-7695-0104-4
This paper presents the VHDL design of a prototype test processor, which can be used for functional testing of digital ICs. The design of the test processor supports itself to be controlled by a microcomputer. The processor can generate mixed-mode (pseudo-random followed by deterministic) test vectors and can apply them to circuit under test (CUT). The test processor also receives the output responses of the CUT and compresses them to a signature. The signature is then sent to the computer for comparison. The test processor supports the testing of combinational as well as sequential circuits (with scan-path).
Citation:
Md. Altaf-Ul-Amin, Zahari Mohamed Darus, "VHDL Design of a Test Processor Based on Mixed-Mode Test Generation," glsvlsi, pp.244, Ninth Great Lakes Symposium on VLSI, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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