Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs

G
GLSVLSI
1999
Ninth Great Lakes Symposium on VLSI
Abstract - Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs

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Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	I. Lemberski, "Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs," Great Lakes Symposium on VLSI, pp. 242, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757424, author = {I. Lemberski}, title = {Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {242}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757424}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs SN - 1066-1395 SP EP A1 - I. Lemberski, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

I. Lemberski, Riga Aviation University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757424

Logic synthesis method for heterogeneous LUT FPGAs implementation is proposed. As an example, XILINX4000 architecture is considered. The method takes XILINX4000 architectural features (heterogeneous LUTs of 3 and 4 inputs) into account and includes two step decomposition. In the first step, two-level logic representation is transformed into a graph of at most 4 fanin nodes (after this step, each node can be mapped onto 4 input LUT). In the second step, selected 4 fanin nodes are re-decomposed into 3 fanin nodes to ensure mapping onto 3 input LUTs. Re-decomposition task is formulated as substituting node two fanins for exactly one fanin.

Citation:

I. Lemberski, "Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs," glsvlsi, pp.242, Ninth Great Lakes Symposium on VLSI, 1999

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