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Ninth Great Lakes Symposium on VLSI
A Multiple-Input Single-Phase Clock Flip-Flop Family
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
x 
 
Richard F. Hobson, Allan R. Dyck, "A Multiple-Input Single-Phase Clock Flip-Flop Family," Great Lakes Symposium on VLSI, pp. 240, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757423,
author = {Richard F. Hobson and Allan R. Dyck},
title = {A Multiple-Input Single-Phase Clock Flip-Flop Family},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {240},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757423},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A Multiple-Input Single-Phase Clock Flip-Flop Family
SN - 1066-1395
SP
EP
A1 - Richard F. Hobson,
A1 - Allan R. Dyck,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Richard F. Hobson, Simon Fraser University
Allan R. Dyck, Simon Fraser University
The design of a versatile CMOS semi-static true single-phase clock flip-flop family is presented. It naturally supports multiple, multiplexed, inputs. Asynchronous Set/Reset are easily implemented. Switching power is lower than for some other semi-static flip-flop techniques.
Citation:
Richard F. Hobson, Allan R. Dyck, "A Multiple-Input Single-Phase Clock Flip-Flop Family," glsvlsi, pp.240, Ninth Great Lakes Symposium on VLSI, 1999
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