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Ninth Great Lakes Symposium on VLSI
Modell Evaluation Using Genetic Manipulation Techniques
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
H.-Ch. Dahmen, The German National Research Center for Information Technology (GMD)
U. Glaeser, The German National Research Center for Information Technology (GMD)
Z. Stamenkovic, University of Nis
Formal Verification is an important area in industry with getting more and more attention. Growing complexity of digital circuits and the use in safety critical systems are the reasons for the need of tools for checking the correctness of designs.In this paper we present a new approach for model evaluation. With our approach we are able to increase the belief of a designer in the right functionality of a circuit without the long runtimes of classical model checking but with more reliability than testing a design via simulation with some input patterns.To achieve this goal we use our genetic manipulation technique: a combination of classical genetic algorithms with a goal oriented mutation operator.
Citation:
H.-Ch. Dahmen, U. Glaeser, Z. Stamenkovic, "Modell Evaluation Using Genetic Manipulation Techniques," glsvlsi, pp.224, Ninth Great Lakes Symposium on VLSI, 1999
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