Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation

G
GLSVLSI
1999
Ninth Great Lakes Symposium on VLSI
Abstract - Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Shugang Wei Articles by Kensuke Shimizu

Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	Shugang Wei, Kensuke Shimizu, "Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation," Great Lakes Symposium on VLSI, pp. 218, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757414, author = {Shugang Wei and Kensuke Shimizu}, title = {Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {218}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757414}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation SN - 1066-1395 SP EP A1 - Shugang Wei, A1 - Kensuke Shimizu, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Shugang Wei, Gunma University

Kensuke Shimizu, Gunma University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757414

Residue arithmetic circuits based on radix-2 signed- digit(SD) number representation, using integers 2pand 2p ? 1 as moduli of residue number system(RNS), are presented. The modulo m addition, m = 2p or m = 2p ? 1, is performed by a carry-free SD adder and the modulo m multiplier is constructed using a binary modulo m SD adder tree. The implementation for the residue arithmetic circuits with VHDL description is proposed. The modulo m adders and multipliers have about 530 and 5000 gates, respectively, in cases of m = 216 ? 1.

Citation:

Shugang Wei, Kensuke Shimizu, "Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation," glsvlsi, pp.218, Ninth Great Lakes Symposium on VLSI, 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.