Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops

G
GLSVLSI
1999
Ninth Great Lakes Symposium on VLSI
Abstract - Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops

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Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri, "Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops," Great Lakes Symposium on VLSI, pp. 140, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757396, author = {Abhijit Ghosh and Sandeep K. Lodha and Ranga Vemuri}, title = {Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {140}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757396}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops SN - 1066-1395 SP EP A1 - Abhijit Ghosh, A1 - Sandeep K. Lodha, A1 - Ranga Vemuri, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Abhijit Ghosh, University of Cincinnati

Sandeep K. Lodha, University of Cincinnati

Ranga Vemuri, University of Cincinnati

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757396

This paper presents a resource-constrained scheduling algorithm for hierarchical behavioral specifications containing nested loops. The algorithm attempts to share resources across levels, to schedule operations that belong to different levels of the nested loop structures in the specifications as well as operations that belong to the same level. We compare the results of scheduling using our algorithm with those obtained using traditional list scheduling with no sharing of resources among different levels of the specification. These results show an average improvement of 23.47% in terms of number of control steps.

Citation:

Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri, "Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops," glsvlsi, pp.140, Ninth Great Lakes Symposium on VLSI, 1999

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