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Ninth Great Lakes Symposium on VLSI
Novel Design for Testability of a Mixed-Signal VLSI IC
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
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E. McShane, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, W.C. Fang, "Novel Design for Testability of a Mixed-Signal VLSI IC," Great Lakes Symposium on VLSI, pp. 97, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757385,
author = {E. McShane and K. Shenai and L. Alkalai and E. Kolawa and V. Boyadzhyan and B. Blaes and W.C. Fang},
title = {Novel Design for Testability of a Mixed-Signal VLSI IC},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {97},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757385},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Novel Design for Testability of a Mixed-Signal VLSI IC
SN - 1066-1395
SP
EP
A1 - E. McShane,
A1 - K. Shenai,
A1 - L. Alkalai,
A1 - E. Kolawa,
A1 - V. Boyadzhyan,
A1 - B. Blaes,
A1 - W.C. Fang,
PY - 1999
KW - Mixed-signal VLSI
KW - testability
KW - verification
KW - microprocessor
KW - RF
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
E. McShane, University of Illinois at Chicago
K. Shenai, University of Illinois at Chicago
L. Alkalai, California Institute of Technology
E. Kolawa, California Institute of Technology
V. Boyadzhyan, California Institute of Technology
B. Blaes, California Institute of Technology
W.C. Fang, California Institute of Technology
A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolation between the circuit-under-test and idle circuits.
Index Terms:
Mixed-signal VLSI, testability, verification, microprocessor, RF
Citation:
E. McShane, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, W.C. Fang, "Novel Design for Testability of a Mixed-Signal VLSI IC," glsvlsi, pp.97, Ninth Great Lakes Symposium on VLSI, 1999
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