Ninth Great Lakes Symposium on VLSI Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation Ann Arbor, Michigan March 04-March 06 ISBN: 0-7695-0104-4
This paper presents a novel analytical approach to compute the switching activity in digital circuits at the word-level in the presence of glitching and correlation. The proposed approach makes use of signal statistics such as mean, variance, and autocorrelation. A novel expression is derived for the switching activity a? at the output node ? of an arbitrary circuit in terms of time-slot autocorrelation coefficient, the expected value, and the signal probability. The switching activity analysis of a signal at the word-level is computed by summing the activities of all the individual bits constituting the signal. A novel relationship between the correlation coefficient of the higher order bits of a normally distributed signal and the bit where the correlation begins is also presented. The proposed approach can estimate the switching activity in less than a second which is orders of magnitude faster than simulation based approaches. Simulation results show that the errors using the proposed approach are about 6% on an average and that the approach is well suited even for highly correlated speech and music signals.
Citation:
Janardhan H. Satyanarayana, Keshab K. Parhi, "Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation," glsvlsi, pp.46, Ninth Great Lakes Symposium on VLSI, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||