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Ninth Great Lakes Symposium on VLSI
The Design of a Register Renaming Unit
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
ASCII Text
x 
 
Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin, "The Design of a Register Renaming Unit," Great Lakes Symposium on VLSI, pp. 34, Ninth Great Lakes Symposium on VLSI, 1999.
 
 
BibTex
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@article{ 10.1109/GLSV.1999.757371,
author = {Benjamin Bishop and Thomas P. Kelliher and Mary Jane Irwin},
title = {The Design of a Register Renaming Unit},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1999},
issn = {1066-1395},
pages = {34},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757371},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - The Design of a Register Renaming Unit
SN - 1066-1395
SP
EP
A1 - Benjamin Bishop,
A1 - Thomas P. Kelliher,
A1 - Mary Jane Irwin,
PY - 1999
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Benjamin Bishop, Pennsylvania State University
Thomas P. Kelliher, Pennsylvania State University
Mary Jane Irwin, Pennsylvania State University
Register renaming is often used to improve performance in many high-ILP processors. However, there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.
Citation:
Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin, "The Design of a Register Renaming Unit," glsvlsi, pp.34, Ninth Great Lakes Symposium on VLSI, 1999
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