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Ninth Great Lakes Symposium on VLSI
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
Aamir A. Farooqui, University of California at Davis
Vojin G. Oklobdzija, University of California at Davis and Integration Berkeley
In this paper, design and VLSI Implementation of an Early Branch Prediction (EBP) circuit, based on a variation of Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2 ?log n/2 ? + 1), and high modularity. This design out performs all the EBP designs presented so far. For 64-bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2- mm technology under typical conditions. Simulation and layout results for 0.2- mm CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results.
Citation:
Aamir A. Farooqui, Vojin G. Oklobdzija, "VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing," glsvlsi, pp.30, Ninth Great Lakes Symposium on VLSI, 1999
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