Functional ATPG for Delay Faults

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	Similar Articles Articles by S. Tragoudas Articles by M. Michael

Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	S. Tragoudas, M. Michael, "Functional ATPG for Delay Faults," Great Lakes Symposium on VLSI, pp. 16, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757367, author = {S. Tragoudas and M. Michael}, title = {Functional ATPG for Delay Faults}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {16}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757367}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Functional ATPG for Delay Faults SN - 1066-1395 SP EP A1 - S. Tragoudas, A1 - M. Michael, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

S. Tragoudas, The University of Arizona

M. Michael, The University of Arizona

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757367

This paper presents a functional level ATPG tool for delay faults which handles all existing fault models. The tool generates patterns using either binary decision diagrams or boolean satisfiability. Experimental results are presented on the ISCAS'85 benchmarks.

Citation:

S. Tragoudas, M. Michael, "Functional ATPG for Delay Faults," glsvlsi, pp.16, Ninth Great Lakes Symposium on VLSI, 1999

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