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Ninth Great Lakes Symposium on VLSI
On Applying Set Covering Models to Test Set Compaction
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
Paulo F. Flores, Cadence European Labs/INESC
Horácio C. Neto, Cadence European Labs/INESC
João P. Marques-Silva, Cadence European Labs/INESC
Test set compaction is a fundamental problem in digital system testing. In recent years, many competitive solutions have been proposed, most of which based on heuristics approaches. This paper studies the application of set covering models to the compaction of test sets, which can be used with any heuristic test set compaction procedure. For this purpose, recent and highly effective set covering algorithms are used. Experimental evidence suggests that the size of computed test sets can often be reduced by using set covering models and algorithms. Moreover, a noteworthy empirical conclusion is that it may be preferable not to use fault simulation when the final objective is test set compaction.
Index Terms:
Test Pattern Generation, Test Set Compaction, Set Covering, Unate Covering Problem
Citation:
Paulo F. Flores, Horácio C. Neto, João P. Marques-Silva, "On Applying Set Covering Models to Test Set Compaction," glsvlsi, pp.8, Ninth Great Lakes Symposium on VLSI, 1999
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