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Ninth Great Lakes Symposium on VLSI
PASTA: Partial Scan to Enhance Test Compaction
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
Irith Pomeranz, University of Iowa
Sudhakar M. Reddy, University of Iowa
We propose a procedure to select flip-flops for partial scan the reduction of test length. We show that cant reductions in test length can be achieved by this cedure. In addition, experimental results show that using heuristics that target the test length does not have to increase the numbers of flip-flops that need to be scanned in order to achieve a given level of fault coverage. quently, it may be possible to perform partial scan selection targeting the two parameters, test length and fault coverage, without requiring more flip-flops than required for one of the parameters.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "PASTA: Partial Scan to Enhance Test Compaction," glsvlsi, pp.4, Ninth Great Lakes Symposium on VLSI, 1999
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