Great Lakes Symposium on VLSI '98 Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example Lafayette, Louisiana February 19-February 24 ISBN: 0-8186-8409-7
This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 Audio/Video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well.
Index Terms:
MPEG, VLSI Design, Top-Down, System Simulation, CAD, Performance modeling, Hardware/Software Co-design, Cycle based simulation
Citation:
Dale E. Hocevar, Ching-Yu Hung, Dan Pickens, Sundararajan Sriram, "Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example," glsvlsi, pp.400, Great Lakes Symposium on VLSI '98, 1998 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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