Great Lakes Symposium on VLSI '98 Stochastic Evolution Algorithm For Technology Mapping Lafayette, Louisiana February 19-February 24 ISBN: 0-8186-8409-7
A new technology mapper (SELF-Map) for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) is described. SELF-Map is based on the Stochastic Evolution (SE) algorithm. The state space model of the problem is defined and suitable cost function which allows optimization for area, delay, or area-delay combinations is proposed. Experimental results show that SELF-Map has an overall better performance compared to other algorithms reported in the literature.
Index Terms:
FPGA, Technology mapping, Stochastic Evolution, Boolean Network, Logic Synthesis.
Citation:
Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef, "Stochastic Evolution Algorithm For Technology Mapping," glsvlsi, pp.380, Great Lakes Symposium on VLSI '98, 1998 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||