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Great Lakes Symposium on VLSI '98
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches
Lafayette, Louisiana
February 19-February 24
ISBN: 0-8186-8409-7
ASCII Text
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Rajesh Raina, Robert Molyneaux, "Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches," Great Lakes Symposium on VLSI, pp. 222, Great Lakes Symposium on VLSI '98, 1998.
 
 
BibTex
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@article{ 10.1109/GLSV.1998.665230,
author = {Rajesh Raina and Robert Molyneaux},
title = {Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1998},
issn = {1066-1395},
pages = {222},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1998.665230},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches
SN - 1066-1395
SP
EP
A1 - Rajesh Raina,
A1 - Robert Molyneaux,
PY - 1998
KW - High-Level Design Validation
KW - Silicon Validation
KW - Pseudo-Random Testing
KW - Microprocessor Testing
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Rajesh Raina, Motorola Inc.
Robert Molyneaux, IBM Corporation
This paper describes a novel method for generating test stimuli for digital systems. By taking advantage of certain properties of the Design Under Validation, the method can be used to generate test stimuli that is "random" as well as "self-testing". We discuss the requirements and limitations of this method on practical designs. The use of this method for High-Level Design Validation of caches in PowerPC (tm) microprocessors is also described. The paper concludes by identifying areas where further work is needed.
Index Terms:
High-Level Design Validation, Silicon Validation, Pseudo-Random Testing, Microprocessor Testing
Citation:
Rajesh Raina, Robert Molyneaux, "Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches," glsvlsi, pp.222, Great Lakes Symposium on VLSI '98, 1998
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