A new approach to modeling the decoding hierarchy in a hierarchical word line (HWL) SRAM architecture using integer-linear programming (ILP) is introduced. Using this approach, the HWL architecture is shown to be inadequate for very large SRAM sizes. Alternatively, a new low-power high- speed SRAM architecture is described. This archtiecture is shown to have fairly constant speed and power dissipation for sizes ranging between 32kb to 4Mb. Low-power is achieved by a voltage boosing technique not requiring a two-step voltage, and by a new mathod of tristating memory cells during a write operation. The SRAM was implemented in a 0.35um CMOS technology operated at 150MHz while dissipating only 10mW.