Parallel VLSI Architectures for Cryptographic Systems

G
GLSVLSI
1997
7th Great Lakes Symposium on VLSI
Abstract - Parallel VLSI Architectures for Cryptographic Systems

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7th Great Lakes Symposium on VLSI

Urbana, IL

March 13-March 15

ISBN: 0-8186-7904-2

	ASCII Text	x
	Fabio Ancona, Alessandro de Gloria, Rodolfo Zunino, "Parallel VLSI Architectures for Cryptographic Systems," Great Lakes Symposium on VLSI, pp. 176, 7th Great Lakes Symposium on VLSI, 1997.

	BibTex	x
	@article{ 10.1109/GLSV.1997.580537, author = {Fabio Ancona and Alessandro de Gloria and Rodolfo Zunino}, title = {Parallel VLSI Architectures for Cryptographic Systems}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1997}, issn = {1066-1395}, pages = {176}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580537}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Parallel VLSI Architectures for Cryptographic Systems SN - 1066-1395 SP EP A1 - Fabio Ancona, A1 - Alessandro de Gloria, A1 - Rodolfo Zunino, PY - 1997 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Fabio Ancona, DIBE - University of Genoa

Alessandro de Gloria, DIBE - University of Genoa

Rodolfo Zunino, DIBE - University of Genoa

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580537

This paper describes a parallel VLSI implementation of a private-key cryptographic system based on Peano- Hilbert curves. The basic unit of the VLSI architecture is the Crypto Processor, that is an SIMD composed of a grid of 256x256 processing units performing elementary operations of encoding process. The key length of the system, measured as number of free parameters, depends linearly on hardware complexity: the cryptographic system is modular and its implementation is very cheap. The CP has been implemented as a single chip with a 1-micron CMOS technology and shows a working frequency of 30 MHz. The chip can be used in consumer applications as well as add-on whenever a certain degree of safety in communication is required.

Citation:

Fabio Ancona, Alessandro de Gloria, Rodolfo Zunino, "Parallel VLSI Architectures for Cryptographic Systems," glsvlsi, pp.176, 7th Great Lakes Symposium on VLSI, 1997

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