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7th Great Lakes Symposium on VLSI
Algorithm and Hardware Support for Branch Anticipation
Urbana, IL
March 13-March 15
ISBN: 0-8186-7904-2
Ted Zhihong Yu, University of Notre Dame
Edwin H.-M. Sha, University of Notre Dame
Nelson Passos, Midwestern State University
Roy Dz-ching Ju, Hewlett-Packard Company
Multi-dimensional systems containing nested loops are widely used to model scientific applications such as image processing, geophysical signal processing and fluid dynamics. However, branches within these loops may degrade the performance of pipelined architectures. This paper presents the theory, supporting hardware and experiments of a novel technique, based on multi-dimensional retiming, for reducing pipeline hazards caused by branches within nested loops. This technique, called ``Multi-Dimensional Branch Anticipation Scheduling'', is able to achieve near-optimal schedule length for nested loops containing branch instructions. It transforms a multi-dimensional conditional data flow graph representing the problem, carries out conditional resource sharing and reduces additional hardware requirements incurred by propagation of branch control signals along the schedule. Such propagation is accomplished by ``Branch Anticipation Bits'' (babits). We further analyze the intricacies of branch anticipation control logic and show that the incurred hardware complexity is low. Thus we demonstrate the efficiency of the algorithm and feasibility of hardware support through a series of experiments.
Citation:
Ted Zhihong Yu, Edwin H.-M. Sha, Nelson Passos, Roy Dz-ching Ju, "Algorithm and Hardware Support for Branch Anticipation," glsvlsi, pp.163, 7th Great Lakes Symposium on VLSI, 1997
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