A prototype chipset for a large scaleable ATM switching node

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	Similar Articles Articles by M. Weeks Articles by M.B. Maaz Articles by H. Krishnamurthy Articles by P. Shipley Articles by M. Bayoumi

7th Great Lakes Symposium on VLSI

Urbana, IL

March 13-March 15

ISBN: 0-8186-7904-2

	ASCII Text	x
	M. Weeks, M.B. Maaz, H. Krishnamurthy, P. Shipley, M. Bayoumi, "A prototype chipset for a large scaleable ATM switching node," Great Lakes Symposium on VLSI, pp. 131, 7th Great Lakes Symposium on VLSI, 1997.

	BibTex	x
	@article{ 10.1109/GLSV.1997.580521, author = {M. Weeks and M.B. Maaz and H. Krishnamurthy and P. Shipley and M. Bayoumi}, title = {A prototype chipset for a large scaleable ATM switching node}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1997}, issn = {1066-1395}, pages = {131}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580521}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - A prototype chipset for a large scaleable ATM switching node SN - 1066-1395 SP EP A1 - M. Weeks, A1 - M.B. Maaz, A1 - H. Krishnamurthy, A1 - P. Shipley, A1 - M. Bayoumi, PY - 1997 KW - CMOS digital integrated circuits; prototype chipset; large scaleable ATM switching node; banyan network; CMOS IC; static logic; dynamic logic; register file; packet headers storage; 1 micron VL - 0 JA - Great Lakes Symposium on VLSI ER -

M. Weeks, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

M.B. Maaz, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

H. Krishnamurthy, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

P. Shipley, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

M. Bayoumi, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580521

This paper presents a chipset for a 16/spl times/16 switching node for the distributed banyan network. This chipset enables the use of a larger and much more efficient switching node than was previously available. Very high performance is required of the chips and thus a number of special circuits have been designed to achieve this performance. The chipset resulting from this design consumes low power. The chips have been designed in 1.0 micron CMOS using a mixture of static and dynamic logic. To achieve the speed needed for a larger node, a register file has been employed to store the packet headers on the control chip. It has an area of 3,150/spl times/3,750 micron, and uses 130,000 transistors. The SRAM blocks on the switch chip, which store a bit-slice of the packets, uses 228,600 transistors.

Index Terms:

CMOS digital integrated circuits; prototype chipset; large scaleable ATM switching node; banyan network; CMOS IC; static logic; dynamic logic; register file; packet headers storage; 1 micron

Citation:

M. Weeks, M.B. Maaz, H. Krishnamurthy, P. Shipley, M. Bayoumi, "A prototype chipset for a large scaleable ATM switching node," glsvlsi, pp.131, 7th Great Lakes Symposium on VLSI, 1997

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