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7th Great Lakes Symposium on VLSI
A new method for asynchronous pipeline control
Urbana, IL
March 13-March 15
ISBN: 0-8186-7904-2
S.S. Appleton, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
S.V. Morton, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
M.J. Liebelt, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
We explore the potential for enhanced performance in asynchronous pipelines by the elimination of unnecessary signalling from the critical path, thus making the common case fast. An improvement of 15% over an optimal two-phase signalling approach for both static and dynamic logic control is demonstrated. We describe extensions to the approach that add functionality with no cycle time overhead.
Index Terms:
asynchronous circuits; asynchronous pipeline control; static logic control; dynamic logic control; VLSI architecture; flow controlled asynchronous method
Citation:
S.S. Appleton, S.V. Morton, M.J. Liebelt, "A new method for asynchronous pipeline control," glsvlsi, pp.100, 7th Great Lakes Symposium on VLSI, 1997
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