VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support

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	Similar Articles Articles by F. Ancona Articles by G . Oddone Articles by S Rovetta Articles by G. Uneddu Articles by R. Zunino

7th Great Lakes Symposium on VLSI

Urbana, IL

March 13-March 15

ISBN: 0-8186-7904-2

	ASCII Text	x
	F. Ancona, G . Oddone, S Rovetta, G. Uneddu, R. Zunino, "VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support," Great Lakes Symposium on VLSI, pp. 94, 7th Great Lakes Symposium on VLSI, 1997.

	BibTex	x
	@article{ 10.1109/GLSV.1997.580417, author = {F. Ancona and G . Oddone and S Rovetta and G. Uneddu and R. Zunino}, title = {VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1997}, issn = {1066-1395}, pages = {94}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580417}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support SN - 1066-1395 SP EP A1 - F. Ancona, A1 - G . Oddone, A1 - S Rovetta, A1 - G. Uneddu, A1 - R. Zunino, PY - 1997 VL - 0 JA - Great Lakes Symposium on VLSI ER -

F. Ancona, DIBE - Dept. of Biophysical and Electronic Eng. University of Genoa

G . Oddone, DIBE - Dept. of Biophysical and Electronic Eng. University of Genoa

S Rovetta, DIBE - Dept. of Biophysical and Electronic Eng. University of Genoa

G. Uneddu, DIBE - Dept. of Biophysical and Electronic Eng. University of Genoa

R. Zunino, DIBE - Dept. of Biophysical and Electronic Eng. University of Genoa

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580417

The paper describes VLSI architectures for sorting analog quantities. The elementary circuit unit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design and enables multi-chip integration. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.

Citation:

F. Ancona, G . Oddone, S Rovetta, G. Uneddu, R. Zunino, "VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support," glsvlsi, pp.94, 7th Great Lakes Symposium on VLSI, 1997

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