A general technique to reduce the energy used by individual CMOS logic gates in large fan-in logic arrays is derived. A fairly small subset of the array inputs is used to do a partial calculation, the results of which can be used to significantly reduce energy use in the rest of the array by avoiding unnecessary charge/discharge cycles. This can be done without significantly reducing the speed, leading to a vastly improved energy-delay product in certain applications such as a PLA and a comparator array. Estimates of the optimal location of the partition and the performance gain as a function of various parameters of the logic array are provided.