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7th Great Lakes Symposium on VLSI
Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks
Urbana, IL
March 13-March 15
ISBN: 0-8186-7904-2
Cristiana Bolchini, Politecnico di Milano
Fabio Salice, Politecnico di Milano
Donatella Sciuto, Politecnico di Milano
A new methodology for designing Totally Self-Checking combinational circuits through the encoding of the Primary Outputs with the Parity code is here presented. The Parity code requires that each fault modifies an odd number of outputs for providing its detection, that is, each fault has to be oddly observable. The proposed methodology for fulfilling such a constraint consists of a post-synthesis modification of fault observability through either the introduction of an auxiliary out-put for the examined network node or the replication of the investigated node. A cost evaluation function allows to select the most convenient solution in terms of overhead and the final 100% TSC circuit.
Citation:
Cristiana Bolchini, Fabio Salice, Donatella Sciuto, "Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks," glsvlsi, pp.32, 7th Great Lakes Symposium on VLSI, 1997
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