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7th Great Lakes Symposium on VLSI
A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems
Urbana, IL
March 13-March 15
ISBN: 0-8186-7904-2
ASCII Text
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J. Navarro, Jr., R. Silveira, F.L. Romao, W.A.M. Van Noije, "A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems," Great Lakes Symposium on VLSI, pp. 14, 7th Great Lakes Symposium on VLSI, 1997.
 
 
BibTex
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@article{ 10.1109/GLSV.1997.580404,
author = {J. Navarro, Jr. and R. Silveira and F.L. Romao and W.A.M. Van Noije},
title = {A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1997},
issn = {1066-1395},
pages = {14},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580404},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems
SN - 1066-1395
SP
EP
A1 - J. Navarro, Jr.,
A1 - R. Silveira,
A1 - F.L. Romao,
A1 - W.A.M. Van Noije,
PY - 1997
KW - CMOS logic circuits; CMOS driver; ECL systems; output buffer; speed performance; effective length; circuit operation; current source switching; output load; SDH/SONET system; CMOS-ECL convertor output buffer; 0.8 mum; 0.7 mum; 1.4 Gbit/s; 50 ohm
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
J. Navarro, Jr., Lab. de Sistemas Integraveis, Sao Paulo Univ., Brazil
R. Silveira, Lab. de Sistemas Integraveis, Sao Paulo Univ., Brazil
F.L. Romao, Lab. de Sistemas Integraveis, Sao Paulo Univ., Brazil
W.A.M. Van Noije, Lab. de Sistemas Integraveis, Sao Paulo Univ., Brazil
This paper presents an output buffer which converts CMOS into ECL levels, and a brief analysis of its speed performance. The structure is designed in a 0.8 /spl mu/m CMOS process (effective length is 0.7 /spl mu/m). The circuit operation is based on current source switching. In the speed analysis we show that the speed is severely limited by the output load, and that the process, for common applications, is a secondary factor. Experimental results for the buffer operating at 1.4 Gbit/s rate are shown. The circuit is part of a 1.2 Gbit/s SDH/SONET system.
Index Terms:
CMOS logic circuits; CMOS driver; ECL systems; output buffer; speed performance; effective length; circuit operation; current source switching; output load; SDH/SONET system; CMOS-ECL convertor output buffer; 0.8 mum; 0.7 mum; 1.4 Gbit/s; 50 ohm
Citation:
J. Navarro, Jr., R. Silveira, F.L. Romao, W.A.M. Van Noije, "A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems," glsvlsi, pp.14, 7th Great Lakes Symposium on VLSI, 1997
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