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6th Great Lakes Symposium on VLSI
An Efficient Multiple Scan Chain Testing Scheme
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
x 
 
Zaifu Zhang, Robert D. McLeod, "An Efficient Multiple Scan Chain Testing Scheme," Great Lakes Symposium on VLSI, pp. 0294, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
x
 
@article{ 10.1109/GLSV.1996.497636,
author = {Zaifu Zhang and Robert D. McLeod},
title = {An Efficient Multiple Scan Chain Testing Scheme},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {0294},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497636},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - An Efficient Multiple Scan Chain Testing Scheme
SN - 0-8186-7502-0
SP
EP
A1 - Zaifu Zhang,
A1 - Robert D. McLeod,
PY - 1996
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Zaifu Zhang, The University of Manitoba
Robert D. McLeod, The University of Manitoba
In this paper an improved multiple scan chain testing scheme to enhance stuck-at and delay fault testing is proposed. With judicial selection of taps from an n stage CA generator, correlation within a multiple input scan chain is reduced. Adopting the multiple scan chains fed by the selected taps of the CA generator also eases the difficulty of arranging shift register latches (SRLs) for scan based pseudo-exhaustive stuck-at fault testing.
Citation:
Zaifu Zhang, Robert D. McLeod, "An Efficient Multiple Scan Chain Testing Scheme," glsvlsi, pp.0294, 6th Great Lakes Symposium on VLSI, 1996
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