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6th Great Lakes Symposium on VLSI
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
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Jai-Sop Hyun, Kwang Sub Yoon, "A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load," Great Lakes Symposium on VLSI, pp. 260, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497630,
author = {Jai-Sop Hyun and Kwang Sub Yoon},
title = {A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {260},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497630},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load
SN - 0-8186-7502-0
SP
EP
A1 - Jai-Sop Hyun,
A1 - Kwang Sub Yoon,
PY - 1996
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
A low voltage Analog CMOS current-mode continuous time high frequency filter with a negative resistance load (NRL) is proposed. To design a current integrator, we use a modified simple current mirror with a NRL to increase the output resistance. The current integrator is designed to have the frequency behavior enhancement and operate in low voltage by employing a simple mirror structure and diode connected input transistor. The third order Butterworth low pass filter using a current integrator is Synthesized and simulated with a 1.5μ n-well process. Simulation result shows cutofj-equency of 50 MHz and power consumption of 2.4mW/pole with a 3Vpower supply.
Citation:
Jai-Sop Hyun, Kwang Sub Yoon, "A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load," glsvlsi, pp.260, 6th Great Lakes Symposium on VLSI, 1996
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