Gray code addressing is one of the techniques previously proposed to reduce switching activity on high capacitance address bus lines. However in order to convert a system to gray address encoding there are several issues a designer needs to consider. This paper analyzes two issues which include gray code encodings for counter increments other than one and tradeoffs in power consumption incurred due to code conversions (binary to gray, gray to binary) when considering address increments and adders. Results show that little penalties are incurred for gray code encoding with increments other than one. Using adders with converters require the bus capacitance to be above 15pf for the configuration to benefit in energy. The best topology is one where gray code encoding is done on off-chip busses.