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6th Great Lakes Symposium on VLSI
Low-Power Implementation of Discrete Cosine Transform
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
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Emad N. Farag, Mohamed I. Elmasry, "Low-Power Implementation of Discrete Cosine Transform," Great Lakes Symposium on VLSI, pp. 0174, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497615,
author = {Emad N. Farag and Mohamed I. Elmasry},
title = {Low-Power Implementation of Discrete Cosine Transform},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {0174},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497615},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Low-Power Implementation of Discrete Cosine Transform
SN - 0-8186-7502-0
SP
EP
A1 - Emad N. Farag,
A1 - Mohamed I. Elmasry,
PY - 1996
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
The demand for multimedia mobile terminals has created a need for low power implementation of video compression algorithms. In this paper we consider different implementations for the discrete cosine transform. The effect of pipelining and parallelism on reducing the power dissipation is considered for fast discrete cosine transform algorithms, as well as ROM-based algorithms.
Citation:
Emad N. Farag, Mohamed I. Elmasry, "Low-Power Implementation of Discrete Cosine Transform," glsvlsi, pp.0174, 6th Great Lakes Symposium on VLSI, 1996
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