loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
6th Great Lakes Symposium on VLSI
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
John Lillis, University of California, San Diego
Chung-Kuan Cheng, University of California, San Diego
Ting-Ting Y. Lin, University of California, San Diego
We present an algorithm for simultaneously finding a Rectilinear Steiner Tree T and buffer insertion points into T. The objective of the algorithm is to minimize a cost function (e.g., total area or power) subject to given timing constraints on the sinks of the net. An interesting side-effect of our approach is that we are able to derive an entire cost/delay tradeoff curve for added flexibility. The solutions produced by the algorithm are optimal subject to the constraint that the routing topology be induced by a permutation on the sinks of the net. We show that high quality sink permutations can be derived from a given routing structure such as the Minimum Spanning Tree. This derivation provides an error bound on the minimum area solution induced by the permutation. The effectiveness of our algorithm is demonstrated experimentally.
Index Terms:
Physical Layout, Timing Optimization, Routing, Buffer Insertion
Citation:
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, "Simultaneous Routing and Buffer Insertion for High Performance Interconnect," glsvlsi, pp.0148, 6th Great Lakes Symposium on VLSI, 1996
Usage of this product signifies your acceptance of the Terms of Use.