Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model

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	Similar Articles Articles by Masato Edahiro Articles by Richard J. Lipton

6th Great Lakes Symposium on VLSI

Ames, IA

March 22-March 23

ISBN: 0-8186-7502-0

	ASCII Text	x
	Masato Edahiro, Richard J. Lipton, "Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model," Great Lakes Symposium on VLSI, pp. 0143, 6th Great Lakes Symposium on VLSI, 1996.

	BibTex	x
	@article{ 10.1109/GLSV.1996.497610, author = {Masato Edahiro and Richard J. Lipton}, title = {Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1996}, isbn = {0-8186-7502-0}, pages = {0143}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497610}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model SN - 0-8186-7502-0 SP EP A1 - Masato Edahiro, A1 - Richard J. Lipton, PY - 1996 KW - VLSI KW - CAD KW - Layout KW - Clock KW - Buffer KW - Placement VL - 0 JA - Great Lakes Symposium on VLSI ER -

Masato Edahiro, C&C Research Laboratories

Richard J. Lipton, Princeton University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497610

A clock buffer placement algorithm is proposed for future technologies in which wire delay dominates signal delay. In such technologies, buffers need to be placed so as to minimize the maximum wire delay. We formulate the problem into a non-linear programming, and solve it by an iteration method with a randomized technique. We applied our buffer placement algorithm with a zero-skew router to several benchmark data, and show that our algorithm achieves 30% less delay time than a H-tree based algorithm.

Index Terms:

VLSI, CAD, Layout, Clock, Buffer, Placement

Citation:

Masato Edahiro, Richard J. Lipton, "Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model," glsvlsi, pp.0143, 6th Great Lakes Symposium on VLSI, 1996

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