Logic Synthesis for Testability

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	Similar Articles Articles by Chien-Chung Tsai Articles by Malgorzata Marek-Sadowska

6th Great Lakes Symposium on VLSI

Ames, IA

March 22-March 23

ISBN: 0-8186-7502-0

	ASCII Text	x
	Chien-Chung Tsai, Malgorzata Marek-Sadowska, "Logic Synthesis for Testability," Great Lakes Symposium on VLSI, pp. 0118, 6th Great Lakes Symposium on VLSI, 1996.

	BibTex	x
	@article{ 10.1109/GLSV.1996.497605, author = {Chien-Chung Tsai and Malgorzata Marek-Sadowska}, title = {Logic Synthesis for Testability}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1996}, isbn = {0-8186-7502-0}, pages = {0118}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497605}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Logic Synthesis for Testability SN - 0-8186-7502-0 SP EP A1 - Chien-Chung Tsai, A1 - Malgorzata Marek-Sadowska, PY - 1996 KW - Logic synthesis KW - Fixed-Polarity Reed-Muller Forms KW - Testability VL - 0 JA - Great Lakes Symposium on VLSI ER -

Chien-Chung Tsai, University of California, Santa Barbara, CA 93106

Malgorzata Marek-Sadowska, University of California, Santa Barbara, CA 93106

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497605

This paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit. A predetermined set of input patterns is applied to identify redundancies and serves as the test set for the resulting circuit. Therefore, test pattern generation is not needed. Experimental results show that our method produces circuits with area comparable to Berkeley SIS 1.2.

Index Terms:

Logic synthesis, Fixed-Polarity Reed-Muller Forms, Testability

Citation:

Chien-Chung Tsai, Malgorzata Marek-Sadowska, "Logic Synthesis for Testability," glsvlsi, pp.0118, 6th Great Lakes Symposium on VLSI, 1996

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