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6th Great Lakes Symposium on VLSI
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
S. Tahar, University of Montreal
Z. Zhou, University of Montreal
X. Song, University of Montreal
E. Cerny, University of Montreal
Michel Langevin, GMD-SET, Shloss Birlinghoven, 53757 St. Augustin, Germany
In this paper we present our results on formally verifying the implementation of an Asynchronous Transfer Mode (ATM) network switching fabric using a new class of decision graphs, called Multiway Decision Graphs (MDG). The design we consider is in use for real applications in the Cambridge Fairisle network. We produced the description of the hardware implementation at different levels of abstraction. We then performed the verification of an abstract description model against the description of the gate-level implementation. Using this abstract model, we accomplished the verification of specific properties that reflect the behavior of the Fairisle ATM switch fabric.
Index Terms:
Hardware Verification, ATM Switch Fabric, Multiway Decision Graphs, Safety Property Checking, Abstract State Machines
Citation:
S. Tahar, Z. Zhou, X. Song, E. Cerny, Michel Langevin, "Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs," glsvlsi, pp.0106, 6th Great Lakes Symposium on VLSI, 1996
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