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6th Great Lakes Symposium on VLSI
A High Speed VLSI Architecture for Scaleable ATM Switches
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
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Paul Shipley, Sherif Sayed, Magdi Bayoumi, "A High Speed VLSI Architecture for Scaleable ATM Switches," Great Lakes Symposium on VLSI, pp. 72, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497596,
author = {Paul Shipley and Sherif Sayed and Magdi Bayoumi},
title = {A High Speed VLSI Architecture for Scaleable ATM Switches},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {72},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497596},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A High Speed VLSI Architecture for Scaleable ATM Switches
SN - 0-8186-7502-0
SP
EP
A1 - Paul Shipley,
A1 - Sherif Sayed,
A1 - Magdi Bayoumi,
PY - 1996
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
This paper presents a prototype of a VLSI chip to be used as a building block for an efficiently scaleable ATM switch with a link speed of 622.2 Mb/s. The chip is a 4x4 shared multibuffer ATM switch based on the distributing banyan architecture. It is efficient in storage space like a shared memory switch and scaleable in size like a space division switch. Since the architecture is self-routing, the chip contains all necessary routing control. Special high speed and low power circuitry is used. The chip is implemented in 1.0 micron static CMOS and measures only 25 mm in area.
Citation:
Paul Shipley, Sherif Sayed, Magdi Bayoumi, "A High Speed VLSI Architecture for Scaleable ATM Switches," glsvlsi, pp.72, 6th Great Lakes Symposium on VLSI, 1996
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