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6th Great Lakes Symposium on VLSI
A Minimum-Area Floorplanning Algorithm for MBC Designs
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
x 
 
Dinesh P. Mehta, Naveed Sherwani, "A Minimum-Area Floorplanning Algorithm for MBC Designs," Great Lakes Symposium on VLSI, pp. 0056, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497593,
author = {Dinesh P. Mehta and Naveed Sherwani},
title = {A Minimum-Area Floorplanning Algorithm for MBC Designs},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {0056},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497593},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A Minimum-Area Floorplanning Algorithm for MBC Designs
SN - 0-8186-7502-0
SP
EP
A1 - Dinesh P. Mehta,
A1 - Naveed Sherwani,
PY - 1996
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Dinesh P. Mehta, University of Tennessee Space Institute
Naveed Sherwani, Intel Corporation
Abstract: This paper identifies important objectives that an MBC floorplanner using flexible, arbitrary rectilinear shapes for standard cell regions should achieve including area minimization, proximity, and connectivity. It then presents an algorithm that guarantees area minimization and connectivity and gives good results with respect to proximity.
Citation:
Dinesh P. Mehta, Naveed Sherwani, "A Minimum-Area Floorplanning Algorithm for MBC Designs," glsvlsi, pp.0056, 6th Great Lakes Symposium on VLSI, 1996
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