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6th Great Lakes Symposium on VLSI
An Accurate Interconnection Length Estimation for Computer Logic
Ames, IA
March 22-March 23
ISBN: 0-8186-7502-0
ASCII Text
x 
 
Dirk Stroobandt, Herwig van Marck, Jan van Campenhout, "An Accurate Interconnection Length Estimation for Computer Logic," Great Lakes Symposium on VLSI, pp. 0050, 6th Great Lakes Symposium on VLSI, 1996.
 
 
BibTex
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@article{ 10.1109/GLSV.1996.497592,
author = {Dirk Stroobandt and Herwig van Marck and Jan van Campenhout},
title = {An Accurate Interconnection Length Estimation for Computer Logic},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1996},
isbn = {0-8186-7502-0},
pages = {0050},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497592},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - An Accurate Interconnection Length Estimation for Computer Logic
SN - 0-8186-7502-0
SP
EP
A1 - Dirk Stroobandt,
A1 - Herwig van Marck,
A1 - Jan van Campenhout,
PY - 1996
KW - Interconnection length
KW - Interconnection complexity
KW - Rent's rule
KW - Donath's hierarchical placement technique
KW - Global interconnection length distribution.
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
Dirk Stroobandt, University of Ghent, Department of Electronics and Information Systems
Herwig van Marck, University of Ghent, Department of Electronics and Information Systems
Jan van Campenhout, University of Ghent, Department of Electronics and Information Systems
Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally obtained average lengths [2]. Yet, this upper bound deviates from the experimentally obtained value by a factor of approximately 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process. [2] W. E. Donath. Placement and average interconnection lengths of computer logic. IEEE Transactions on Circuits & Systems, CAS-26: pages 272-277, 1979.
Index Terms:
Interconnection length, Interconnection complexity, Rent's rule, Donath's hierarchical placement technique, Global interconnection length distribution.
Citation:
Dirk Stroobandt, Herwig van Marck, Jan van Campenhout, "An Accurate Interconnection Length Estimation for Computer Logic," glsvlsi, pp.0050, 6th Great Lakes Symposium on VLSI, 1996
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