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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
A new look at the conditions for the synthesis of speed-independent circuits
The State University of New York at Buffalo
March 16-March 18
ISBN: 0-8186-7035-5
ASCII Text
x 
 
E. Pastor, J. Cortadella, O. Roig, "A new look at the conditions for the synthesis of speed-independent circuits," Great Lakes Symposium on VLSI, pp. 230, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516058,
author = {E. Pastor and J. Cortadella and O. Roig},
title = {A new look at the conditions for the synthesis of speed-independent circuits},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {230},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516058},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - A new look at the conditions for the synthesis of speed-independent circuits
SN - 1066-1395
SP
EP
A1 - E. Pastor,
A1 - J. Cortadella,
A1 - O. Roig,
PY - 1995
KW - integrated logic circuits; VLSI; logic CAD; circuit CAD; integrated circuit design; logic design; circuit optimisation; speed-independent circuits; gate-level synthesis; gate library constraint; optimization techniques; fan-in reduction
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
E. Pastor, Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain
J. Cortadella, Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain
O. Roig, Dept. of Comput. Archit., universitat Politecnica de Catlunya, Barcelona, Spain
This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures that use simple AND-gates, and do not exploit the advantages offered by the existence of complex gates. The use of complex gates increases the speed and reduces the area of the circuits. These improvements are achieved because of (1) the elimination of the distributivity, signal persistency and unique minimal state requirements imposed by other techniques; (2) the reduction in the number of internal signals necessary to guarantee the synthesis; and finally (3) the utilization of optimization techniques to reduce the fan-in of the involved gates and the number of required memory elements.
Index Terms:
integrated logic circuits; VLSI; logic CAD; circuit CAD; integrated circuit design; logic design; circuit optimisation; speed-independent circuits; gate-level synthesis; gate library constraint; optimization techniques; fan-in reduction
Citation:
E. Pastor, J. Cortadella, O. Roig, "A new look at the conditions for the synthesis of speed-independent circuits," glsvlsi, pp.230, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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