loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Parallel hierarchical global routing for general cell layout
The State University of New York at Buffalo
March 16-March 18
ISBN: 0-8186-7035-5
ASCII Text
x 
 
S. Khanna, S. Gao, K. Thulasiraman, "Parallel hierarchical global routing for general cell layout," Great Lakes Symposium on VLSI, pp. 212, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
x
 
@article{ 10.1109/GLSV.1995.516055,
author = {S. Khanna and S. Gao and K. Thulasiraman},
title = {Parallel hierarchical global routing for general cell layout},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {212},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516055},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Parallel hierarchical global routing for general cell layout
SN - 1066-1395
SP
EP
A1 - S. Khanna,
A1 - S. Gao,
A1 - K. Thulasiraman,
PY - 1995
KW - network routing; VLSI; circuit layout CAD; integrated circuit layout; integer programming; parallel algorithms; parallel hierarchical global routing; general cell layout; routing algorithm; hierarchical decomposition strategy; parallel processing; integer programming; network flow optimization; shared-memory machine
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
S. Khanna, Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
S. Gao, Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
K. Thulasiraman, Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine and experiment results on different examples show relative speedup between 4 and 5 for 8 processors. The speedup is achieved without compromising the quality of the routing results.
Index Terms:
network routing; VLSI; circuit layout CAD; integrated circuit layout; integer programming; parallel algorithms; parallel hierarchical global routing; general cell layout; routing algorithm; hierarchical decomposition strategy; parallel processing; integer programming; network flow optimization; shared-memory machine
Citation:
S. Khanna, S. Gao, K. Thulasiraman, "Parallel hierarchical global routing for general cell layout," glsvlsi, pp.212, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.