Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Statistical estimation of delay fault detectabilities and fault grading
The State University of New York at Buffalo
March 16-March 18
ISBN: 0-8186-7035-5
Zaifu Zhang, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
R.D. McLeod, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
G.E. Bridges, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
In this paper, we present a statistical delay fault estimation technique. The basic method is an extension of STAFAN to include delay faults. A strategy to calculate the transition observabilities of fanout stems is proposed. Correlation within each fanout free region is considered in calculating gate line transition controllabilities. Results show this is a practical method of calculating detectabilities of delay faults. When compared with transition delay fault simulations, the estimations of fault coverage are within 2.3% for the benchmark circuits. Finally, the estimation technique is used to grade delay faults, with comparison to fault simulation results used to validate the method.
Index Terms:
fault diagnosis; logic testing; statistical analysis; VLSI; statistical estimation; delay fault detectabilities; fault grading; STAFAN; transition observabilities; fanout stems; fanout free region; gate line transition controllabilities; fault coverage; benchmark circuits; logic testing
Citation:
Zaifu Zhang, R.D. McLeod, G.E. Bridges, "Statistical estimation of delay fault detectabilities and fault grading," glsvlsi, pp.184, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995