Technology mapping algorithms for sequential circuits using look-up table based FPGAS

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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	S. Habib, Quan Xu, "Technology mapping algorithms for sequential circuits using look-up table based FPGAS," Great Lakes Symposium on VLSI, pp. 164, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516045, author = {S. Habib and Quan Xu}, title = {Technology mapping algorithms for sequential circuits using look-up table based FPGAS}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {164}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516045}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Technology mapping algorithms for sequential circuits using look-up table based FPGAS SN - 1066-1395 SP EP A1 - S. Habib, A1 - Quan Xu, PY - 1995 KW - sequential circuits; table lookup; field programmable gate arrays; delays; network routing; flip-flops; circuit layout CAD; logic CAD; technology mapping algorithms; sequential circuits; look-up table; FPGAS; time delay; routing results; flip-flops; adjacent combinational parts VL - 0 JA - Great Lakes Symposium on VLSI ER -

S. Habib, Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA

Quan Xu, Dept. of Comput. Sci., Graduate Sch. of City Univ. of New York, NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516045

This paper presents a set of algorithms for mapping sequential circuits onto look-up table based FPGAs and explores how it is possible to reduce the time delay and simplify the final routing results of this mapping. We define several new terms which are used to describe the problem. This work focuses on the mapping of flip-flops and their adjacent combinational parts in sequential circuits using LUT based FPGAs.

Index Terms:

sequential circuits; table lookup; field programmable gate arrays; delays; network routing; flip-flops; circuit layout CAD; logic CAD; technology mapping algorithms; sequential circuits; look-up table; FPGAS; time delay; routing results; flip-flops; adjacent combinational parts

Citation:

S. Habib, Quan Xu, "Technology mapping algorithms for sequential circuits using look-up table based FPGAS," glsvlsi, pp.164, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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