Priority driven channel pin assignment

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by I. Peters Articles by P. Molitor

Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	I. Peters, P. Molitor, "Priority driven channel pin assignment," Great Lakes Symposium on VLSI, pp. 132, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516039, author = {I. Peters and P. Molitor}, title = {Priority driven channel pin assignment}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {132}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516039}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Priority driven channel pin assignment SN - 1066-1395 SP EP A1 - I. Peters, A1 - P. Molitor, PY - 1995 KW - network routing; integrated circuit layout; VLSI; circuit layout CAD; computational complexity; polynomial time improvement; linear channel pin assignment; LCPA algorithms; minimum channel density; priority schedule; vertical constraints; priority driven channel pin assignment; channel height; running time; VLSI; channel routing VL - 0 JA - Great Lakes Symposium on VLSI ER -

I. Peters, Inst. fur Inf., Halle Univ., Germany

P. Molitor, Inst. fur Inf., Halle Univ., Germany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516039

We present a polynomial time improvement of the linear channel pin assignment LCPA algorithms presented by Cai and Wong in 1990. We solve the LCPA problem according to minimum channel density under a special priority schedule subject to vertical constraints and flux. The priority driven linear channel pin assignment algorithm (PDCPA) reduces the channel height by an average of 17% without increasing the running time.

Index Terms:

network routing; integrated circuit layout; VLSI; circuit layout CAD; computational complexity; polynomial time improvement; linear channel pin assignment; LCPA algorithms; minimum channel density; priority schedule; vertical constraints; priority driven channel pin assignment; channel height; running time; VLSI; channel routing

Citation:

I. Peters, P. Molitor, "Priority driven channel pin assignment," glsvlsi, pp.132, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.