Performance driven standard-cell placement using the genetic algorithm

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	Similar Articles Articles by H. Youssef Articles by S.M. Sait Articles by K. Nassar Articles by M.S.T. Benten

Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	H. Youssef, S.M. Sait, K. Nassar, M.S.T. Benten, "Performance driven standard-cell placement using the genetic algorithm," Great Lakes Symposium on VLSI, pp. 124, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516037, author = {H. Youssef and S.M. Sait and K. Nassar and M.S.T. Benten}, title = {Performance driven standard-cell placement using the genetic algorithm}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {124}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516037}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Performance driven standard-cell placement using the genetic algorithm SN - 1066-1395 SP EP A1 - H. Youssef, A1 - S.M. Sait, A1 - K. Nassar, A1 - M.S.T. Benten, PY - 1995 KW - cellular arrays; genetic algorithms; timing; integrated circuit layout; delays; logic CAD; circuit layout CAD; standard-cell placement; genetic algorithm; area; connection length; timing performance; timing-driven placer; IC design; wire length; propagation delays; critical paths; /spl alpha/-criticality; delay performance improvement VL - 0 JA - Great Lakes Symposium on VLSI ER -

H. Youssef, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

S.M. Sait, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

K. Nassar, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

M.S.T. Benten, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516037

Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of /spl alpha/-criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20%.

Index Terms:

cellular arrays; genetic algorithms; timing; integrated circuit layout; delays; logic CAD; circuit layout CAD; standard-cell placement; genetic algorithm; area; connection length; timing performance; timing-driven placer; IC design; wire length; propagation delays; critical paths; /spl alpha/-criticality; delay performance improvement

Citation:

H. Youssef, S.M. Sait, K. Nassar, M.S.T. Benten, "Performance driven standard-cell placement using the genetic algorithm," glsvlsi, pp.124, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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