An efficient building block layout methodology for compact placement

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	Similar Articles Articles by N.G. Bourbakis Articles by M. Mortazavi

Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	N.G. Bourbakis, M. Mortazavi, "An efficient building block layout methodology for compact placement," Great Lakes Symposium on VLSI, pp. 118, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516036, author = {N.G. Bourbakis and M. Mortazavi}, title = {An efficient building block layout methodology for compact placement}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {118}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516036}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - An efficient building block layout methodology for compact placement SN - 1066-1395 SP EP A1 - N.G. Bourbakis, A1 - M. Mortazavi, PY - 1995 KW - circuit layout CAD; network routing; formal languages; VLSI; integrated circuit layout; integrated circuit interconnections; building block layout methodology; compact placement; synthesis placement; compaction; formal language; GEOMETRIA; geometric reshapings; VLSI regulation; functional performance; connection lines; occupied chip area; neighboring relations; dead space; open holes; channels merging process; legal overlapping; local routing; global routing VL - 0 JA - Great Lakes Symposium on VLSI ER -

N.G. Bourbakis, T.J. Watson Sch. of Appl. Sci., Binghamton Univ., NY, USA

M. Mortazavi, T.J. Watson Sch. of Appl. Sci., Binghamton Univ., NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516036

In this paper, a new efficient methodology for building block layout is presented by using synthesis placement and compaction. The synthesis placement part of the methodology is based on a formal language called GEOMETRIA. The compaction part is based on geometric reshapings (gs) of blocks and the merging of the communication channels. Both reshaping and merging follow the VLSI regulations for legal layout placement and improve the overall functional performance of the integrated system, by reducing the average length of the connection lines and the size of the occupied chip area by retaining the functionality and the neighboring relations of the blocks. The main goal of the blocks' geometric reshaping is minimization of the wasted area (or dead space among the blocks) called "open holes". The channels merging process of compaction is based on the legal overlapping of the blocks' communication channels by reducing the layout placement at the local and global routing.

Index Terms:

circuit layout CAD; network routing; formal languages; VLSI; integrated circuit layout; integrated circuit interconnections; building block layout methodology; compact placement; synthesis placement; compaction; formal language; GEOMETRIA; geometric reshapings; VLSI regulation; functional performance; connection lines; occupied chip area; neighboring relations; dead space; open holes; channels merging process; legal overlapping; local routing; global routing

Citation:

N.G. Bourbakis, M. Mortazavi, "An efficient building block layout methodology for compact placement," glsvlsi, pp.118, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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