Synthesis of SEU-tolerant ASICs using concurrent error correction

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	Similar Articles Articles by H. Hollander Articles by B.S. Carlson Articles by T.D. Bennett

Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	H. Hollander, B.S. Carlson, T.D. Bennett, "Synthesis of SEU-tolerant ASICs using concurrent error correction," Great Lakes Symposium on VLSI, pp. 90, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516031, author = {H. Hollander and B.S. Carlson and T.D. Bennett}, title = {Synthesis of SEU-tolerant ASICs using concurrent error correction}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {90}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516031}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Synthesis of SEU-tolerant ASICs using concurrent error correction SN - 1066-1395 SP EP A1 - H. Hollander, A1 - B.S. Carlson, A1 - T.D. Bennett, PY - 1995 KW - radiation hardening (electronics); application specific integrated circuits; logic partitioning; sequential circuits; error correction codes; Hamming codes; logic CAD; circuit layout CAD; SEU-tolerant ASIC synthesis; concurrent error correction; single event upsets; memory elements; single error correction/double error detection Hamming code; area overhead; delay overhead; memory element set partitioning; design experiments; sequential circuit; fault tolerant design VL - 0 JA - Great Lakes Symposium on VLSI ER -

H. Hollander, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

B.S. Carlson, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

T.D. Bennett, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516031

We present a new design technique for the concurrent error correction of single event upsets in the memory elements of ASICs. The technique uses a single error correction/double error detection (SEC/DED) Hamming code to encode the content of the memory elements. The area and delay overhead and error-correction capability are optimized by partitioning the set of memory elements. Design experiments show our technique is feasible, and it can be applied to any ASIC technology.

Index Terms:

radiation hardening (electronics); application specific integrated circuits; logic partitioning; sequential circuits; error correction codes; Hamming codes; logic CAD; circuit layout CAD; SEU-tolerant ASIC synthesis; concurrent error correction; single event upsets; memory elements; single error correction/double error detection Hamming code; area overhead; delay overhead; memory element set partitioning; design experiments; sequential circuit; fault tolerant design

Citation:

H. Hollander, B.S. Carlson, T.D. Bennett, "Synthesis of SEU-tolerant ASICs using concurrent error correction," glsvlsi, pp.90, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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