Symbolic execution of data paths

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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	C. Monahan, F. Brewer, "Symbolic execution of data paths," Great Lakes Symposium on VLSI, pp. 80, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516029, author = {C. Monahan and F. Brewer}, title = {Symbolic execution of data paths}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {80}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516029}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Symbolic execution of data paths SN - 1066-1395 SP EP A1 - C. Monahan, A1 - F. Brewer, PY - 1995 KW - data flow graphs; data flow analysis; hazards and race conditions; Boolean functions; constraint handling; combinational switching; combinational circuits; logic design; processor scheduling; digital signal processing chips; symbolic execution; data-path model; path constraints; bus hazards; register constraints; control encoding limitations; Boolean functions; dataflow graphs; path-constrained model; scheduling; DSP microprocessor; memory elements; switching logic; combinational logic; connection constraints; operand constraints VL - 0 JA - Great Lakes Symposium on VLSI ER -

C. Monahan, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

F. Brewer, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516029

We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor.

Index Terms:

data flow graphs; data flow analysis; hazards and race conditions; Boolean functions; constraint handling; combinational switching; combinational circuits; logic design; processor scheduling; digital signal processing chips; symbolic execution; data-path model; path constraints; bus hazards; register constraints; control encoding limitations; Boolean functions; dataflow graphs; path-constrained model; scheduling; DSP microprocessor; memory elements; switching logic; combinational logic; connection constraints; operand constraints

Citation:

C. Monahan, F. Brewer, "Symbolic execution of data paths," glsvlsi, pp.80, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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