A two-stage simulated annealing methodology

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by J.M. Varanelli Articles by J.P. Cohoon

Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	J.M. Varanelli, J.P. Cohoon, "A two-stage simulated annealing methodology," Great Lakes Symposium on VLSI, pp. 50, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516023, author = {J.M. Varanelli and J.P. Cohoon}, title = {A two-stage simulated annealing methodology}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {50}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516023}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - A two-stage simulated annealing methodology SN - 1066-1395 SP EP A1 - J.M. Varanelli, A1 - J.P. Cohoon, PY - 1995 KW - simulated annealing; circuit optimisation; VLSI; circuit CAD; integrated circuit design; two-stage simulated annealing methodology; formal method; starting temperature determination; optimization problems; adaptive schedules; stop criterion; running time; problem suite; VLSI; CAD VL - 0 JA - Great Lakes Symposium on VLSI ER -

J.M. Varanelli, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

J.P. Cohoon, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516023

We propose a two-stage simulated annealing method. While most previous work has focused on ad hoc constant starting temperatures for the low temperature annealing phase, this paper presents a more formal method for starting temperature determination in two-stage simulated annealing systems. We have successfully applied our method to three optimization problems using both classic and adaptive schedules. We also briefly discuss an alternative stop criterion that experimentally reduces the running time up to an additional ten percent in our problem suite.

Index Terms:

simulated annealing; circuit optimisation; VLSI; circuit CAD; integrated circuit design; two-stage simulated annealing methodology; formal method; starting temperature determination; optimization problems; adaptive schedules; stop criterion; running time; problem suite; VLSI; CAD

Citation:

J.M. Varanelli, J.P. Cohoon, "A two-stage simulated annealing methodology," glsvlsi, pp.50, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.