Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
A scalable analog architecture for neural networks with on-chip learning and refreshing
The State University of New York at Buffalo
March 16-March 18
ISBN: 0-8186-7035-5
B.A. Alhalabi, Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
M. Bayoumi, Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
This paper discusses various techniques for analog storage and handling and proposes a new class of architecture suitable for modular and scalable analog neural networks with on-chip learning and refreshing. The new architecture is based on analog functional blocks and analog pass switches which enhance the system versatility. Supporting algorithms are also developed. A novel characteristic is the full-analog on-chip learning methodology which substantially increases the learning speed. The speedup is evidenced by the utilization of local analog synaptic updating scheme which utterly eliminates time-sharing components. Moreover, this localization scheme conceives unbounded scalability in this neural architecture.
Index Terms:
analogue processing circuits; neural chips; learning (artificial intelligence); analogue storage; scalable analog architecture; neural networks; on-chip learning; on-chip refreshing; analog storage; analog functional blocks; analog pass switches; system versatility; learning speed; local analog synaptic updating scheme; unbounded scalability
Citation:
B.A. Alhalabi, M. Bayoumi, "A scalable analog architecture for neural networks with on-chip learning and refreshing," glsvlsi, pp.33, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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