We present algorithms to perform power-driven partitioning and formulate two applications within this domain: chip-level power management for multi-FPGA systems and single chip power optimization using localized voltage scaling. We tested the effectiveness of our approach on a set of LUT-level benchmark netlists. Savings in power consumption with our approach are 19.18% (as high as 32.28) and 14.78 % on average (as high as 25.79%) when partitioning is performed under resource constraints. If the number of partitions is not restricted, power improvements as high as 54 % are achievable.