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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)
Napa, California
April 20-April 23
ISBN: 0-7695-2230-0
Jianchun Li, Case Western Reserve University, Cleveland, OH
Christos Papachristou, Case Western Reserve University, Cleveland, OH
Raj Shekhar, Cleveland Clinic Foundation, Cleveland, OH
In this paper, we present a reconfigurable SoC (system-on-chip) architecture and a 3D caching scheme, targeted to Virtex II Pro FPGAs, to accelerate a broad range of 3D medical imaging algorithms, typically dominated by local operations. To achieve high computational bandwidth, architectural parallelisms are exploited at three different levels: brick operation cycle, multiple parallel data-stream processing and deep pipeline architecture for data-stream processing.
Citation:
Jianchun Li, Christos Papachristou, Raj Shekhar, "A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing," fccm, pp.320-321, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004
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